Job Description Summary
The software development group of Custom Structured ASIC Engineering (CSAE) develops design tools and methodologies for designing with Structured ASIC devices.
These products straddle the design space between FPGAs and ASICs and bring to chip designers the best of both worlds.
As a member of the Software QA team within this group, you will work with rest of the team to assist in several aspects of QA and testing of the design software tools (called eTools) developed for releasing the software to customers.
You will develop test cases for testing the design flow through eTools and architectural features of the structured ASICs as needed.
You will assist in developing and deploying automation for testing the tools and design flows. You will write scripts, develop small-scale IP-blocks and test benches as needed.
Develop test cases for testing design flow and architectural features of the Structured ASIC
Test new features implemented in the Software tools developed for each release, this may include automated testing or manual testing as needed
Perform regression testing of individual tools and design flows, analyze results and validate the software for final release to customers
Report bugs for the test failures in the Issue-Tracking System, track the bug fixes and verify them
Qualifications - Essential :
BS or MS in Electrical Engineering, Computer engineering or related areas
At least 2 years’ experience in ASIC or FPGA design flows and tools
Solid knowledge of RTL development and verification methodology employing any HDL, preferably Verilog.
Skilled Linux / Unix environment user
Knowledge of at least one scripting language such as Perl, Tcl or Shell
Ability to communicate well in English
Qualifications - Desirable :
Knowledge of ASIC design flow and tools such as Synopsys Design Compiler, VCS, Prime Time
Experience with automated software testing